Double Edge Triggered Flip Flop

Seminar paper from the year 2013 in the subject Engineering - Computer Engineering, Indian Institute of Technology, Delhi, language: English, abstract: A conventional Flip Flop allows the input data to alter the output either when the clock's input changes from 0 to 1, i.e. from low to high (Positive Edge Triggered Flip Flop) or when the clock's input changes from 1 to 0, i.e. from high to low (Negative Edge Triggered Flip Flop). The output is never altered by the input data on both the clock transitions; i.e. the conventional flip flops can respond to clock at most once per clock cycle. Now, the power consumption of a system becomes a crucial parameter in many applications, hence a Double Edge Triggered Flip Flop is introduced. The proposed Double Edge Triggered Flip Flop would be able to respond to both the edges of the clock pulse and would have definite advantages with respect to speed, data transfer rate, reliability and energy dissipation. This paper aims at using D-Flip Flop to explain and analyze the concept of Double Edge Triggered Flip Flop (As synchronous D-Flip Flop is one of the most fundamental building blocks in modern VLSI systems); discussing three of the recent developments in the field of Double Edge Triggering Mechanism; focusing on some of the drawbacks of this method and providing an alternative approach.