Hardware Design and Petri Nets

Preface. Part I: Hardware Modelling using Petri Nets. 1. Comprehensive Causal Specification of Asynchronous Controller and Arbiter Behaviour; R. Wollowski, J. Beister. 2. Complementing Role Models with Petri Nets in Studying Asynchronous Data Communications; F. Xia, I. Clark. 3. Petri Net Representations of Computational and Communication Operators; D.H. Schaefer, J.H. Sosa. Part II: Model Analysis and Verification for Asynchronous Design. 4. Properties of Change Diagrams; U. Schwiegelshohn, L. Thiele. 5. LTrL-based Model Checking for a Restricted Class of Signal Transition Graphs; R. Meyer, P.S. Thiagarajan. 6. A Polynomial Algorithm to Compute the Concurrency Relation of a Regular STG; A. Kovalyov. Part III: Theory and Practice of Petri Net Based Synthesis. 7. Synthesis of Synchronous Digital Systems Specified by Petri Nets; N. Marranghello, et al. 8. Deriving Signal Transition Graphs from Behavioral Verilog HDL; I. Blunno, L. Lavagno. 9. The Design of the Control Circuits for an Asynchronous Instruction Prefetch Unit Using Signal Transition Graphs; S.-H. Chung, S. Furber. Part IV: Hardware Design Methods and Tools. 10. Electronic System Design Automation Using High Level Petri Nets; P. Rokyta, et al. 11. An Evolutionary Approach to the Use of Petri Net Based Models; R.J. Machado, et al. 12. Modelling and Implementation of Petri Nets Using VHDL; D. Prothero. Part V: Architecture Modelling and Performance Analysis. 13. Performance Analysis of Asynchronous Circuits and Systems using Stochastic Timed Petri Nets; A. Xie, P.A. Beerel. 14. Performance Analysis of Dataflow Architectures Using Timed Coloured Petri Nets; B.R.T.M. Witlox, et al. 15. Modeling a Memory Subsystem with Petri Nets: a Case Study; M. Gries. 16. Performance Modeling of Multithreaded Distributed Memory Architectures; W.M. Zuberek.