Hardware Component Modeling

Series Presentation. Editors. Volume Presentation. 1. The History of VITAL: VHDL ASIC Library Update; V. Berman. 2. Issues in Efficient Modeling and Acceleration of Vital Models; S. Nayak, A. Roy. 3. Standards for Interoperability and Portability; S. Hurat. 4. Abstract Data Types and the Digital System Description and Simulation Environments; P.A. Wilsey, et al. 5. Modeling Highly Flexible and Self-Generating Parameterizable Components in VHDL; V. Preis, S. März- Rössel. 6. Melody: An Efficient Layout-Based Model Generator; F. Delguste, et al. 7. Quality Measures & Analysis: A Way to Improve VHDL Models; M. Mastretti, et al. 8. Modern Concepts of Quality and Their Relationship to Design Reuse and Model Libraries; L. Józwiak. Index.