Offset Reduction Techniques in High-Speed Analog-to-Digital Converters: Analysis, Design and Tradeof
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Beschreibung
Preface. List of Symbols and Abbreviations.
1 High-Speed ADC Architectures. 1.1 Introduction. 1.2 The Analog-to-Digital Converter. 1.3 Flash ADCs. 1.4 Two-Step Flash ADCs. 1.5 Folding and Interpolation ADCs. 1.6 Building Blocks of CMOS High-Speed ADCs.
2 Averaging Technique - DC Analysis and Termination. 2.1 Introduction. 2.2 Published Studies on the Averaging Technique. 2.3 Output Voltage and Gain. 2.4 Effect of Mismatches - INL and DNL. 2.5 Averaging in Folding Circuits. 2.6 Considerations About the Yield. 2.7 Termination of the Averaging Network.
3 Averaging Technique - Transient Analysis and Automated Design. 3.1 Introduction. 3.2 Flash ADC Architecture. 3.3 Output Voltage and Gain. 3.4 Effect of Mismatches. 3.5 Design of Averaged Pre-Amplifier Stages in Flash ADCs.
4 Integrated Prototypes using Averaging. 4.1 Introduction. 4.2 7-bit 120 MS/s I/Q flash ADC. 4.3 10-bit 100 MS/s Folding and Interpolation ADC.
5 Offset Cancellation Methods. 5.1 Introduction. 5.2 Offset Cancellation Techniques. 5.3 New Offset Cancellation Technique. 5.4 6-bit 1 GHz Two-Step Subranging ADC.
6 Conclusions. 6.1 Overview of the Research Work.
Appendix A Averaging with Piecewise Linear Differential Pairs. A.1 Introduction. A.2 Output Voltage and Gain. A.3 Effect of Mismatches - INL and DNL.
Appendix B Mismatches in the Resistors of the Aveaging Network. B.1 Introduction. B.2 Mismatches in Resistors R0. B.3 Mismatches in Resistors R1.
Appendix C Averaging in Folding Stages. C.1 Introduction. C.2 Equivalence Between Circular and Infinite Networks. C.3 Output Voltage and Gain. C.4 Effect of Mismatches.
References. Index.
Eigenschaften
Breite: | 159 |
Gewicht: | 744 g |
Höhe: | 241 |
Länge: | 34 |
Seiten: | 382 |
Sprachen: | Englisch |
Autor: | João C. Vital, Pedro M. Figueiredo |