Closing the Gap Between ASIC & Custom: Tools and Techniques for High-Performance ASIC Design
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Beschreibung
Preface. List of trademarks. 1. Introduction and Overview of the Book; D. Chinnery, K. Keutzer.
Contributing Factors.
2. Improving Performance through Microarchitecture; D. Chinnery, K. Keutzer. 3. Reducing the Timing Overhead; D. Chinnery, K. Keutzer. 4. High-Speed Logic, Circuits, Libraries and Layout; A. Chang, et al. 5. Finding Peak Performance in a Process; D. Chinnery, K. Keutzer.
Design Techniques.
6. Physical Prototyping Plans for High Performance; M. Courtoy, et al. 7. Automatic Replacement of Flip-Flops by Latches in ASIC's; D. Chinnery, et al. 8. Useful-Skew Clock Synthesis Boosts ASIC Performance; W. Dai, D. Staepelaere. 9. Faster and Lower Power Cell-Based Designs with Transistor-Level Cell Sizing; M. Côté, P. Hurat. 10. Design Optimization with Automated Flex-Cell Creation; D. Bhattacharya, V. Boppana. 11. Exploiting Structure and Managing Wires to Increase Density and Performance; A. Chang, W.J. Dally. 12. Semi-Custom Methods in a High-Performance Microprocessor Design; G.A. Northrop. 13. Controlling Uncertainty in High Frequency Designs; S.E. Rich, et al. 14. Increasing Circuit Performance through Statistical Design Techniques; M. Orshansky.
Design Examples.
15. Achieving 550MHz in a Standard Cell ASIC Methodology; D. Chinnery, et al. 16. The iCORE® 520MHz Synthesizable CPU Core; N. Richardson, et al. 17. Creating Synthesizable ARM Processors with Near Custom Performance; D. Flynn, M.Keating.
Contributing Factors.
2. Improving Performance through Microarchitecture; D. Chinnery, K. Keutzer. 3. Reducing the Timing Overhead; D. Chinnery, K. Keutzer. 4. High-Speed Logic, Circuits, Libraries and Layout; A. Chang, et al. 5. Finding Peak Performance in a Process; D. Chinnery, K. Keutzer.
Design Techniques.
6. Physical Prototyping Plans for High Performance; M. Courtoy, et al. 7. Automatic Replacement of Flip-Flops by Latches in ASIC's; D. Chinnery, et al. 8. Useful-Skew Clock Synthesis Boosts ASIC Performance; W. Dai, D. Staepelaere. 9. Faster and Lower Power Cell-Based Designs with Transistor-Level Cell Sizing; M. Côté, P. Hurat. 10. Design Optimization with Automated Flex-Cell Creation; D. Bhattacharya, V. Boppana. 11. Exploiting Structure and Managing Wires to Increase Density and Performance; A. Chang, W.J. Dally. 12. Semi-Custom Methods in a High-Performance Microprocessor Design; G.A. Northrop. 13. Controlling Uncertainty in High Frequency Designs; S.E. Rich, et al. 14. Increasing Circuit Performance through Statistical Design Techniques; M. Orshansky.
Design Examples.
15. Achieving 550MHz in a Standard Cell ASIC Methodology; D. Chinnery, et al. 16. The iCORE® 520MHz Synthesizable CPU Core; N. Richardson, et al. 17. Creating Synthesizable ARM Processors with Near Custom Performance; D. Flynn, M.Keating.
Eigenschaften
Breite: | 155 |
Höhe: | 235 |
Seiten: | 414 |
Sprachen: | Englisch |
Autor: | David Chinnery, Kurt Keutzer |
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