Behavioral Synthesis for Hardware Security

Introduction.- Background.- Techniques for algorithm-level obfuscation during high-level synthesis.- High-level synthesis of key based obfuscated RTL datapaths.- RTL Hardware IP protection Using Key-Based Control and Data Flow Obfuscation.- Empirical Word-Level Analysis of Arithmetic Module Architectures for Hardware Trojan Susceptibility.- Behavioral synthesis techniques for intellectual property protection.- Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis.- High-Level Synthesis for Side-Channel Defense.- On state encoding against power analysis attacks for finite state controllers.- Examining the consequences of high-level synthesis optimizations on power side-channel.- Towards a timing attack aware high-level synthesis of integrated circuits.- High-Level Synthesis with Timing-Sensitive Information Flow Enforcement.- Mitigating information leakage during critical communication using S*FSM.- Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security-Driven Task Scheduling.- Securing industrial control system with high level synthesis.- Conclusions and open research problems.