SVA: The Power of Assertions in SystemVerilog

Part I. Opening.- Introduction.- System Verilog Language and Overview.- System Verilog Simulation Semantics.- Part II. Basic Assertions.- Assertion Statements.- Basic Properties.- Basic Sequences.- Assertion System Functions and Tasks.- Part III. Metalanguage Constructs.- Let, Sequence and Property Declarations; Inference.- Checkers.- Part IV. Advanced Assertions.- Advanced Properties.- Advanced Sequences.- Clocks.- Resets.- Procedural Concurrent Assertions.- An Apology for Local Variables.- Mechanics of Local Variables.- Recursive Properties.- Coverage.- Debugging Assertions and Efficiency Considerations.- Part V. Formal Verification.- Introduction to Assertion-Based Formal Verification.- Formal Verification and Models.- Formal Semantics.- Part VI. Advanced Checkers.- Checkers in Formal Verification.- Checker Libraries.- Appendix.- References.- Index.